Presentation at CAISE 2020 Designing patterns for certification standards and guidelines
Presentation at CAISE 2020 Designing patterns for certification standards and guidelines
The PML analyzer is an open source API providing a simple DSL to build a description of the architecture of your chip based on the PHYLOG Model Language (PML). From this representation a set of safety and interference model templates can be generated to perfom safety and interference analyses of your platform.
It has now migrated to github
https://github.com/onera/pml-analyzer