Hardware resources found in modern processor architecture, such as the memory hierarchy, can improve the performance of a task by anticipating its needs based on its execution history and behaviour. Schedulability analyses and policies tend to ignore such behaviours, in favour of conservative assumptions, as their effects are difficult to assess. When they are included, the analysis can be very complex and the measures needed are hard to obtain. In this presentation, we consider abstract timing models that capture stress and sensitivity with respect to the memory hierarchy, at a lower cost than conservative timing models, and their application to task scheduling.
Lieu : grande salle de réunions du bât. D (au fond du couloir) de l'ONERA à Toulouse.
Lien visio : https://rdv.onera.fr/seminaireDTIS